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quad - channel, 12- bit, serial input, 4 ma to 20 ma output dac with dynamic power control and hart connectivity data sheet ad5737 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no resp onsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 w ww.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features 12- bit resolution and monotonicity dynamic power control for thermal management or external pmos mode current output ranges: 0 ma to 20 ma, 4 ma to 20 ma, and 0 ma to 24 ma 0.1 % total unadjusted error (tue) maximum user - programmable offset and gain on - chip diagnostics on - chip reference : 10 ppm/ c maximum ? 40c to +105c temperature range applications process control actuator control plcs hart network connectivity general description the ad5737 is a quad - channel current output dac that operates with a power supply range from 10.8 v to 33 v . on- chip dynamic power control minimizes package power dissipation by regulating the voltage on the output driver from 7.4 v to 29.5 v using a dc - to - dc boost con verter optimized for minimum on - chip power dissipation. each channe l has a corresponding chart pin so that hart signals can be coupled onto the current output of the ad5737 . the ad5737 uses a versatile 3- wire serial interface that operates at clock rates of up to 30 mhz and is compatible with standard spi, qspi?, microwire ? , dsp, and microcontroller interface standards. the serial interface also features optional crc - 8 packet error checking, as well as a watchdog timer that monitors activity on the interface. product highlights 1. dynamic p ower c ontrol for t hermal m anagement. 2. 12- bit pe rformance. 3. quad c hannel. 4. hart compliant. companion products product family: ad5755 , ad5755 -1 , ad5757 , ad5735 hart modem: ad5700 , ad5700 -1 external references: adr445 , adr02 digital isolators: ADUM1410 , ad um1411 power: adp2302 , adp2303 additional companion products on the ad5737 product page functional block dia gram ad5737 agnd av dd +15v av cc 5.0v dv dd dgnd ldac clear sclk sdin sync sdo f au lt dc- t o-dc converter digi tal inter f ace reference current output range scaling alert refout refin notes 1. x = a, b, c, or d. ad1 ad0 dac a sw x v boost_x gain reg a offset reg a r set_x chartx i out_x dac channe l b dac channe l a dac channe l c dac channe l d 7.4v t o 29.5v + 10067-101 figure 1.
ad5737 data sheet rev. b | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 companion products ....................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 detailed functional block diagram .............................................. 3 specifications ..................................................................................... 4 ac performance characteristics ................................................ 6 timing characteristics ................................................................ 6 absolute maximum ratings ............................................................ 9 thermal resistance ...................................................................... 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 13 curr ent outputs ......................................................................... 13 dc - to - dc converter ................................................................. 17 reference ..................................................................................... 18 general ......................................................................................... 19 terminology .................................................................................... 20 theory of operation ...................................................................... 21 dac architecture ....................................................................... 21 power - on state of the ad5737 ................................................ 21 serial interface ............................................................................ 21 transfer function ....................................................................... 22 registers ........................................................................................... 23 enabling the output ................................................................... 24 reprogramming the output ran ge ......................................... 24 data registers ............................................................................. 25 control registers ........................................................................ 27 readback operation .................................................................. 30 device features ............................................................................... 32 fault output ................................................................................ 32 digital offset and gain co ntrol ............................................... 32 status readback during a write .............................................. 32 asynchronous clear ................................................................... 32 packet error checking ............................................................... 33 watchdog timer ......................................................................... 33 alert output ................................................................................ 33 inte rnal reference ...................................................................... 33 external current setting resistor ............................................ 33 hart connectivity ................................................................... 34 digital slew rate control .......................................................... 34 dynamic power control ............................................................ 35 dc - to - dc converters ............................................................... 35 ai cc supply requirements static .......................................... 36 ai cc supply requirements slewing ...................................... 37 external pmos mode ................................................................ 38 applications information .............................................................. 39 current output mode with internal r set ................................ 39 prec ision voltage reference selection ..................................... 39 driving inductive loads ............................................................ 39 transient voltage protection .................................................... 40 microprocessor interfacing ....................................................... 40 layout guidelines ....................................................................... 40 galvanically isolated interface ................................................. 41 industrial hart capable analog output application ........ 42 outline dimensions ....................................................................... 43 ordering guide .......................................................................... 43 revision history 5 /12 rev. a to rev. b changes to companion products section .................................... 1 change to table 6 ........................................................................... 12 adde d i ndustrial hart c apable a nalog o utput a pplication section and figure 65, renumbered sequentially ..................... 42 updated outline dimensions ....................................................... 43 11/11 rev. 0 to rev. a change to accuracy, external r set parameter in table 1 ............ 4 changes to power - on state of the ad5737 section .................. 21 changes to readback operation section and readback example section ............................................................................. 30 7/ 11 r evision 0: in it ial version
data sheet ad5737 rev. b | page 3 of 44 detailed functional block diagram ad5737 agnd av dd +15v av cc 5.0v dv dd dgnd ldac clear sclk sdin sync sdo f au lt dc- t o-dc converter dynamic power contro l input shift register and contro l sta tus register power-on reset reference buffers v ref wa tchdog timer (spi activity) alert refout refin ad1 ad0 dac a 12 12 sw a v boost_ a gain reg a offset reg a r1 r2 r3 r set_ a char ta i out_b , i out_c , i out_d r set_b , r set_c , r set_d chartb, chartc, chartd i out_ a dac channe l b dac channe l a dac channe l c dac channe l d sw b , sw c , sw d v boost_b , v boost_c , v boost_d 7.4v t o 29.5v v sen1 v sen2 + 10067-001 dac reg a dac input dat a reg a figure 2.
ad5737 data sheet rev. b | page 4 of 44 specifications av dd = v boost_x = 15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc - to - dc converter disabled; agnd = dgnd = gndsw x = 0 v; refin = 5 v; r l = 300 ?; all specifications t min to t max , unless otherwise noted. table 1 . parameter 1 min typ max unit test conditions/comments current output output current ranges 0 24 ma 0 20 ma 4 20 ma resolution 12 bits accurac y , external r set assumes ideal resistor (see the external current setting resistor section for more information) total unadjusted error (tue) ?0.1 0.019 +0.1 % fsr tue long - term stability 100 ppm fsr drif t after 1000 hours, t j = 150c relative accuracy (inl) ?0.032 0.006 +0.032 % fsr differential nonlinearity (dnl) ?1 +1 lsb guaranteed monotonic offset error ?0.1 0.012 +0. 1 % fsr offset error drift 2 4 ppm fsr/c gain error ?0.1 0.004 +0.1 % fsr gain tc 2 3 ppm fsr/c full - scale error ?0.1 0.014 +0. 1 % fsr full - scale tc 2 5 ppm fsr/c dc crosstalk 0.0005 % fsr external r set accuracy, in ternal r set total unadjusted error (tue) 3 , 4 ?0.14 0.022 +0.14 % fsr tue long - term stability 180 ppm fsr drift after 1000 hours, t j = 150c relative accuracy (inl) ?0.032 0.006 +0.032 % fsr differential nonlinearity (dnl) ?1 +1 lsb guarante ed monotonic offset error 3 , 4 ?0.1 0.0 17 +0.1 % fsr offset error drift 2 6 ppm fsr/c gain error ?0.12 0.00 4 +0.12 % fsr gain tc 2 9 ppm fsr/c full - scale error 3 , 4 ?0.14 0.0 2 +0.14 % fsr full - scale tc 2 14 ppm fsr/c dc crosstalk 4 ?0.011 % fsr internal r set output characteristics 2 current loop compliance voltage v bo ost_ x ? 2.4 v boost_x ? 2. 7 v output current drift vs. time drift after 1000 hours, ? scale output, t j = 150c 90 ppm fsr external r set 140 ppm fsr internal r set resistive load 1000 ? the dc - to - dc converter has been characterized with a max imum load of 1 k?, chosen such that compliance is not exceeded; see figure 30 and the dc - dc maxv bits in table 27 dc output impedance 100 m? dc psrr 0.02 1 a/v re ference input/output reference input 2 reference input voltage 4.95 5 5.05 v for specified performance dc input impedance 45 150 m? reference output output voltage 4.995 5 5.005 v t a = 25 c reference tc 2 ?10 5 +10 ppm/c
data sheet ad5737 rev. b | page 5 of 44 parameter 1 min typ max unit test conditions/comments output noise (0.1 hz to 10 hz) 2 7 v p -p noise spectral density 2 100 nv/ hz at 10 khz output voltage drift vs. time 2 180 ppm drift after 1000 hours, t j = 150c capacitive load 2 1000 nf load current 9 ma see figure 41 short - circuit current 10 ma line regulation 2 3 ppm/v see figure 42 load regulation 2 95 ppm/ma see figure 41 thermal hysteresis 2 160 ppm first temperature cycle 5 ppm second temperature cycle dc - to -dc converter switch sw itch on resistance 0.425 ? switch leakage current 10 na peak current limit 0.8 a oscillator oscillator frequency 11.5 13 14.5 mhz this oscillator is divided down to provide the dc -to - dc converter switching frequency maximum duty cycle 89.6 % at 410 khz dc -to - dc switching frequency digital inputs 2 jedec compliant input high voltage , v ih 2 v input low voltage , v il 0.8 v input current ?1 +1 a per pin pin capacitance 2.6 pf per pin digital outputs 2 sdo, alert pins output low voltage, v ol 0.4 v sinking 200 a output high voltage, v oh dv dd ? 0.5 v sourcing 200 a high impedance leakage current ?1 +1 a high im pedance output capacitance 2.5 pf fau lt pin output low voltage, v ol 0.4 v 10 k? pull - up resistor to dv dd 0.6 v at 2.5 ma output high voltage, v oh 3.6 v 10 k? pull - up resistor to dv dd power requirements av dd 9 33 v dv dd 2.7 5.5 v av cc 4.5 5.5 v ai dd 7 7 .5 ma di cc 9.2 11 ma v ih = dv dd , v il = dgnd, internal oscillator running, over supplies ai cc 1 ma output s unloaded, over supplies i boost 5 1 ma per channe l, 0 ma output power dissipation 1 55 mw av dd = 15 v, dv dd = 5 v, dc -to - dc converter enable d , outputs disabled 1 tem perature range: ?40c to +105c; typical at +25c. 2 guaranteed by design and characterization; not production tested. 3 for current outputs with internal r set , the offset, full - scale, and tue measurements exclude dc crosstalk. the measurements are made with all four chan nels enabled and loaded with the same code. 4 see the current output mode with internal r set section for more information about dc crosstalk. 5 efficiency plots in figure 32 through figure 35 include the i boost quiescent current.
ad5737 data sheet rev. b | page 6 of 44 ac performance chara cteristics av dd = v boost_x = 15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc - to - dc converter disabled; agnd = dgnd = gndsw x = 0 v; refin = 5 v; r l = 3 00 ?; all specifications t min to t max , unless otherwise noted. table 2 . parameter 1 min typ max unit test conditions/comments dynamic performance, current output output current settling time 15 s to 0.1% fsr, 0 ma to 24 ma range see test conditions/comments ms for settling times when using the dc - to - dc con - verter, see figure 25 , figure 26 , and figu re 27 output noise (0.1 hz to 10 hz bandwidth) 0.15 lsb p -p 12- bit lsb, 0 ma to 24 ma range output noise spectral density 0.5 na/hz measured at 10 k hz, midscale output, 0 ma to 24 ma range 1 guaranteed by design and characterization; not production tested. timing characteristi cs av dd = v boost_x = 15 v; dv dd = 2.7 v to 5.5 v; av cc = 4.5 v to 5.5 v; dc - to - dc converter disabled; agnd = dgnd = gndsw x = 0 v; refin = 5 v; r l = 300 ?; all specifica tions t min to t max , unless otherwise noted. table 3 . parameter 1, 2, 3 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min syn c falling edge to sclk falling edge setup time t 5 13 ns min 24th/32nd sclk falling edge to sync rising edge (see figure 53 ) t 6 198 ns min sync high time t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 20 s min sync rising edge to ldac falling edge (all dacs updated or any channel has digital slew rate control enabled) 5 s min sync rising edge to ldac falling edge (single dac updated) t 10 10 ns min ldac pulse width low t 11 500 ns max ldac falling edge to dac output response time t 12 see table 2 s max dac output settling time t 13 10 ns min clear high time t 14 5 s max clear activation time t 15 40 ns max sclk rising edge to sdo valid t 16 sync rising edge to dac output response time ( ldac = 0) 21 s min a ll dacs updated 5 s min single dac updated t 17 500 ns min ldac falling edge to sync rising edge t 18 800 ns min reset pulse width t 19 4 sync hig h to next sync low (digital slew rate control enabled) 20 s min all dacs updated 5 s min single dac updated 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with t rise = t f all = 5 ns (10% to 90% of dv dd ) and timed from a voltage level of 1.2 v. 3 see figure 3 , figure 4 , figure 5 , and figure 6 . 4 this specification applies if ldac is held low during the write cycle; otherwise, see t 9 .
data sheet ad5737 rev. b | page 7 of 44 timing diagrams msb sclk sync sdin ldac ldac = 0 clear 1 2 24 lsb t 1 i out_x i out_x i out_x t 4 t 6 t 3 t 2 t 5 t 8 t 7 t 10 t 9 t 10 t 11 t 12 t 12 t 16 t 19 t 17 t 13 reset t 18 t 14 10067-002 figure 3 . serial interface timing diagram sync msb msb lsb lsb input word specifies register t o be read no p condition t 6 t 15 sdin msb lsb undefined selected register d at a clocked out sdo sclk 24 24 1 1 10067-003 figure 4 . readback timing diagram
ad5737 data sheet rev. b | page 8 of 44 sdo disabled r/w sdin sclk sync sdo 1 2 16 l sb msb dut_ ad1 sdo_ enab dut_ ad0 x x x d15 d14 d1 d0 sta tus sta tus sta tus sta tus 10067-004 figure 5 . status readback during write, timing diagram 200 a i ol 200 a i oh v oh (min) or v ol (max) t o output pin c l 50pf 10067-005 figure 6 . load circuit for sdo timing diagram s
data sheet ad5737 rev. b | page 9 of 44 absolute maximum rat ings t a = 25c, unless otherwise n oted. transient currents of up to 100 ma do not cause scr latch - up. table 4 . parameter rating av dd , v boost_x to agnd, dgnd ?0.3 v to +33 v av cc to agnd ?0.3 v to +7 v dv dd to dgnd ?0.3 v to +7 v digital inputs to dgnd ?0.3 v to dv dd + 0.3 v or +7 v (whichever is less) digital outputs to dgnd ?0.3 v to dv dd + 0.3 v or +7 v (whichever is less) refin, refout to agnd ?0.3 v to av dd + 0.3 v or +7 v (whichever is less) i out_x to agnd a gnd to v boost_x or 33 v if using the dc -to - dc c onverter sw x to agnd ?0.3 v to +33 v agnd, gndsw x to dgnd ?0.3 v to +0.3 v operating temperature range (t a ) industrial 1 ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 125c power dissipation (t j max ? t a )/ ja lead temperature jedec industry standard soldering j- std -020 1 power dissipated on chip must be derated to keep the junction temperature below 125c. stresses above those listed under absolute maximum ratings may cause permanent damage to the device . this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods m ay affect device reliability. thermal resistance junction - to - air thermal resist ance ( ja ) is specified for a jedec 4- layer test board. table 5 . thermal resistance package type ja unit 64- lead lfcsp (cp -64-3) 20 c/w esd caution
ad5737 data sheet rev. b | page 10 of 44 pin configuration and function descripti ons 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 dg nd reset av dd nc char ta ig a te a com p dcdc_ a v boost_ a nc i out_ a agnd nc chartb nc ig ateb com p dcdc_b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 r set_c r set_d refout refin nc chartd ig ated com p dcdc_d v boost_d nc i out_d agnd nc chartc nc ig atec 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 r set_b r set_ a refgnd refgnd ad0 ad1 sync sclk sdin sdo dv dd dgnd ldac clear alert f au lt com p dcdc_c i out_c v boost_c av cc sw c gndsw c gndsw d sw d agnd sw a gndsw a gndsw b sw b agnd v boost_b i out_b 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad5737 top view (not to scale) pin 1 indic at or notes 1. nc = no connec t . do not connect t o this pin. 2. the exposed p addle should be connected to agnd, or, al tern a tive ly, it can be left electrical ly unconnected. it is recommended th at the p addle be thermal ly connected to a copper plane for enhanced therma l performance. 10067-006 figure 7 . pin configuration table 6 . pin function descriptions pin no. mnemonic description 1 r set_b a n external, precision, low drift , 15 k ? c urrent setting resistor can be connected to this pin to improve the i out_b temperature drift performance. for more information, see the external current setting resistor section. 2 r set_a a n external, precision, low dri ft , 15 k ? c urrent setting resistor can be connected to this pin to improve the i out_a temperature drift performance. for more information, see the external current setting resistor section. 3 refgnd ground reference point for internal reference. 4 refgnd ground reference point for internal reference. 5 ad0 address decode for the device under test (dut) on the board. 6 ad1 address decode for the dut on the board. 7 sync frame synchronization signal for the serial interface. active l ow i nput. wh en sync is low, data is clocked into the input shift register on the falling edge of sclk. 8 sclk serial clock input. data is clocked into the input shift register on the falling edge of sclk. th e serial interface operates at clock speeds of up to 30 mhz. 9 sdin serial data input. data must be valid on the falling edge of sclk. 10 sdo serial data output. used to clock data from the s erial register in readback mode (s ee figure 4 and figure 5 ). 11 dv dd digital supply pin . the voltage range is from 2.7 v to 5.5 v. 12 dgnd digital ground. 13 ldac load dac . this active low in put is used to update the dac register and , consequently , the dac outputs. when ldac is tied permanently low, the addressed dac data register is updated on the rising edge of sync . if ldac is held high during the write cycle, the dac input register is updated, but the dac output is update d only on the falling edge of ldac (see figure 3 ). using this mode, all analog outputs c an be updated simultaneously. the ldac pin must not be left unconnected.
data sheet ad5737 rev. b | page 11 of 44 pin no. mnemonic description 14 clear active high, edge sensitive input. when this pin is asserted, the output current is set to the programmed clear code bit setting. only channels enabled to be cleared are cleared. for more information, s ee the asynchronous clear section. when clear is active, the dac output register cannot be written to. 15 alert active high output. this pin is asserted when the re is no spi activity on the interface pins for a pre set time. f or more information , see the alert output s ection . 16 fau lt active low, open - drain output. this pin is asserted low when any of the following conditions is detected: open circuit , pec error , or an overtemperature condition (see the fault output section). 17 dgnd digital ground. 18 reset ha rdware reset, active low input. 19 av dd positive analog supply pin . the voltage range is from 9 v to 33 v. 20 nc no connect. do not connect to this pin. 21 charta hart input connection for dac channel a . for more information , see the hart connectivity section. 22 igatea optional connection for external pass transistor. leave this pin unconnected when using the dc -to - dc converter . for more information, s ee the external pmos m ode section . 23 comp dcdc_a dc -to -dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel a dc -to - dc converter. alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin . for more information, see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section . 24 v boost_a supply for channel a current output stage (see figure 48 ). to use the dc -to - dc converter , connect this pin as shown in figure 55 . 25 nc no connect. do not conne ct to this pin. 26 i out_a current output pin for dac channel a. 27 a gnd ground reference point for analog circuitry. this pin must be connected to 0 v. 28 nc no connect. do not connect to this pin. 29 chartb hart input connection for dac channel b. for more information , see the hart connectivity section. 30 nc no connect. do not connect to this pin. 31 igateb optional connection for external pass transistor. leave this pin unconnected when using the dc -to - dc converter. for more information, see the external pmos m ode section . 32 comp dcdc_b dc -to - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel b dc -to - dc converter. alterna tively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin . for more information, see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section . 33 i out_b current output pin for dac channel b. 34 v boost_b supply for channel b current output stage (see figure 48 ). to use the dc -to - dc convert er , connect this pin as shown in figure 55 . 35 agnd ground reference point for analog circuitry. this pin must be connected to 0 v. 36 sw b switching output for channel b dc -to - dc circuitry. to use the dc -to - dc c onverter , connect this pin as shown in figure 55 . 37 gndsw b ground connection for dc - to - dc switching circuit. this pin should always be connected to ground. 38 gndsw a ground connection for dc - to - dc switching cir cuit. this pin should always be connected to ground. 39 sw a switching output for channel a dc -to - dc circuitry. to use the dc -to - dc converter, connect this pin as shown in figure 55 . 40 agnd ground reference point for analog circuitry. this pin must be connected to 0 v. 41 sw d switching output for channel d dc - to - dc circuitry. to use the dc - to - dc converter, connect this pin as shown in figure 55 . 42 gndsw d ground connec tion for dc - to - dc switching circuit. this pin should always be connected to ground. 43 gndsw c ground connection for dc - to - dc switching circuit. this pin should always be connected to ground. 44 sw c switching output for channel c dc -to - dc circuitry. to us e the dc -to - dc converter, connect this pin as shown in figure 55 . 45 av cc supply for dc - to - dc circuitry. the voltage range is from 4.5 v to 5.5 v. 46 v boost_c supply for channel c current output stage (see figure 48 ). to use the dc -to - dc converter, connect this pin as shown in figure 55 . 47 i out_c current output pin for dac channel c. 48 comp dcdc_c dc -to - dc compensation capaci tor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel c dc -to - dc converter. alternatively, if using an external compensation resistor, place a resistor in series with a capacitor to ground from this pin . for more information, see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section .
ad5737 data sheet rev. b | page 12 of 44 pin no. mnemonic description 49 igatec optional connection for external pass transis tor. leave this pin unconnected when using the dc -to - dc converter. for more information, see the external pmos m ode section. 50 nc no connect. do not connect to this pin. 51 chartc hart input connection for dac c hannel c. for more information , see the hart connectivity section. 52 nc no connect. do not connect to this pin. 53 a gnd ground reference point for analog circuitry. this pin must be connected to 0 v. 54 i out_d current output p in for dac channel d. 55 nc no connect. do not connect to this pin. 56 v boost_d supply for channel d current output stage (see figure 48 ). to use the dc -to - dc converter, connect this pin as shown in figure 55 . 57 comp dcdc_d dc -to - dc compensation capacitor. connect a 10 nf capacitor from this pin to ground. used to regulate the feedback loop of the channel d dc - to - dc converter. alternatively, if using an external compens ation resistor, place a resistor in series with a capacitor to ground from this pin . for more information, see the dc -to - dc converter compensation capacitors section and the ai cc supply re quirements slewing section . 58 igated optional connection for external pass transistor. leave this pin unconnected when using the dc -to - dc converter. for more information, see the external pmos m ode section. 59 chartd hart inpu t connection for dac channel d. for more information , see the hart connectivity section. 60 nc no connect. do not connect to this pin. 61 refin external reference voltage input. 62 refout internal reference voltage output. it i s recommended that a 0.1 f capacitor be placed between refout and refgnd. refout must be connected to refin to use the internal reference. 63 r set_d a n external, precision, low drift , 15 k ? c urrent setting resistor can be connected to this pin to improve the i out_d temperature drift performance. for more information, s ee the external current setting resistor section. 64 r set_c a n external, precision, low drift , 15 k ? c urrent setting resistor can be connected to t his pin to improve the i out_c temperature drift performance. for more information, see the external current setting resistor section. epad exposed pad. th e exposed paddle should be connected to agnd , or, alternatively, it can be left electrically unconnected. it is recommended that the pad dle be thermally connected to a copper plane for enhanced thermal performance.
data sheet ad5737 rev. b | page 13 of 44 typical performance characteristics current outputs ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0. 008 0 1000 2000 3000 4000 in l error (%fsr) code av dd = 15 v t a = 2 5c 4m a t o 20 m a, i nt er n al r set 4m a t o 20 m a, extern al r set 4ma t o 20 m a, i nt er n al r set , with dc- t o-d c co n ve rt er 4ma t o 20 m a, ext er n al r set , with d c- t o-dc c on v er t er 10067-231 figure 8. int egral nonlinearity error vs. dac code ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0. 4 0.6 0.8 1.0 0 1000 2000 3000 4000 dn l error (lsb) code av dd = 15 v t a = 2 5c 4m a t o 20 m a, i nt er n al r set 4m a t o 20 m a, extern al r set 4ma t o 20 m a, i nt er n al r set , with dc- t o-d c co n ve rt er 4ma t o 20 m a, ext er n al r set , with d c- t o-dc c on v er t er 10067-232 figure 9. differential nonlinearity error vs. dac code ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0 1000 2000 3000 4000 total unadjusted error (%fsr) code av dd = 15 v t a = 2 5c 10067-233 4m a t o 20 m a, i nt er n al r set 4m a t o 20 m a, interna l r set , with dc- t o- dc co n ver t er 4ma t o 20 m a, ex t er n al r set 4ma t o 20 m a, ext er n al r set , with d c- t o-dc c on v er t er figure 10 . total unadjusted error vs. dac code ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 ?40 ?20 0 20 40 60 80 100 in l error (%fsr) tempera ture (c) 4ma to 20ma r an ge max inl 0ma to 20ma r ange max inl 0ma to 24ma r an ge max inl 4ma to 20ma r ange min inl 0ma to 20ma r an ge min inl 0ma to 24ma r ange min inl av dd = 15 v 10067-234 figure 11 . integral nonlinear ity error vs. temperature, internal r set ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 ?40 ?20 0 20 40 60 80 100 in l error (%fsr) tempera ture (c) 4ma to 20ma r an ge max inl 0ma to 20ma r ange max inl 0ma to 24ma r an ge max inl 4ma to 20ma r ange min inl 0ma to 20ma r an ge min inl 0ma to 24ma r ange min inl av dd = 15 v 10067-235 figure 12 . integral nonlinearity error vs. temperature, external r set ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 ?40 ?20 0 20 40 60 80 100 dn l error (lsb) tempera ture (c) ma x dn l mi n dn l av dd = 15 v al l ranges interna l and externa l r set 10067-236 figure 13 . differential nonlinearity error vs. temperature
ad5737 data sheet rev. b | page 14 of 44 ?0.025 ?0.020 ?0. 015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0.025 tota l unadjusted error (%fsr) ?40 ?20 0 20 40 60 80 100 tempera ture (c) av dd = 15v 10067-155 4m a t o 20m a rang e, interna l r set 4m a t o 20m a range, externa l r set figure 14 . total unadjusted error vs. temperature ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 full-scale error (%fsr) ?40 ?20 0 20 40 60 80 100 t empera ture (c) av dd = 15v 4m a t o 20m a range, interna l r set 4m a t o 20m a range, externa l r set 10067-157 figure 15 . full - scale error vs. temperature ?0.025 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 gain error (%fsr) ?40 ?20 0 20 40 60 80 100 tempera ture (c) av dd = 15v 10067-159 4m a t o 20m a range, interna l r set 4m a t o 20m a range, externa l r set figure 16 . gain error vs. temperature ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 5 10 15 20 25 30 in l error (%fsr) supply (v) min inl max inl t a = 25c 4m a t o 20m a range 10067-240 figure 17 . integral nonlinearity error vs. supply, external r set ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 5 10 15 20 25 30 in l error (%fsr) supply (v) min inl max inl t a = 25c 4m a t o 20m a rang e 10067-241 figure 18 . integral nonlinearity error vs. supply, internal r set ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 5 10 15 20 25 30 dnl error (lsb) supply (v) max dnl min dnl t a = 25c al l ranges 10067-242 figure 19 . differential nonlinearity error vs. supply
data sheet ad5737 rev. b | page 15 of 44 ?0.005 ?0.010 ?0.015 ?0.020 ?0.025 ?0.030 ?0.035 0.005 0 10 5 15 20 25 30 tota l unadjusted error (%fsr) supply (v) 4m a t o 20m a range t a = 25c max tue min tue 10067-060 figure 20 . total unad justed error vs. supply , external r set total unadjusted error (%fsr) 4m a t o 20m a range t a = 25c ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 min tue 10 5 15 20 25 30 supply (v) max tue 10067-061 figure 21 . total unadjusted error vs. supply , internal r set ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 10 15 20 25 30 total unadjusted error (%fsr) v boost_x supply (v) 10067-188 t a = 25c external pmos (ntljs4149) 4ma to 20ma range r load = 300? max tue min tue figure 22 . total unadjusted error vs. v boost_x supply u sing external pmos mode 6 5 4 3 2 1 0 0 20 15 10 5 current (a) time (s) av dd = 15v t a = 25c r load = 300? 10067-062 figure 23 . current vs. time on power - up 4 ?10 ?8 ?6 ?4 ?2 0 2 0 1 2 3 4 5 6 current (a) time (s) av dd = 15v t a = 25c r load = 300? int_enable = 1 10067-063 figure 24 . current vs. time on output enable 0 5 10 15 20 25 30 output current (ma) and v boost_x vo lt age (v) ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 time (ms) 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) av cc = 5v t a = 25c i out_x v boost_x 10067-167 figure 25 . output current and v boost_x settling time with dc -to- dc converter (see figure 55 )
ad5737 data sheet rev. b | page 16 of 44 0 5 10 15 20 25 30 output current (ma) ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 time (ms) t a = ?40c t a = +25c t a = +105c 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) av cc = 5v 10067-168 figure 26 . output current settling time with dc -to- dc converter over temperature (see figure 55 ) 0 5 10 15 20 25 30 output current (ma) ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 time (ms) av cc = 4.5v av cc = 5.0v av cc = 5.5v 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 10067-169 figure 27 . output current settling time with dc -to- dc converter over av cc (see figure 55 ) 0 5 10 15 20 25 ?5 5 0 10 15 20 output current (ma) time (s) 10067-189 i out (4ma to 20ma step) i out (20ma to 4ma step) t a = 25c external pmos (ntljs4149) 4ma to 20ma range r load = 300? v boost_x = 24v figure 28 . output current settling time with external pmos transistor ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 0 2 4 6 8 10 12 14 current (ac-coupled) (a) time (s) av cc = 5v f sw = 410khz induc t or = 10h (xal4040-103) 0m a t o 24m a range 1k? load externa l r set t a = 25c 20m a output 10m a output 10067-170 figure 29 . output cu rrent , ac - coupled vs. time with dc -to- dc converter (see figure 55 ) 8 7 6 5 4 3 2 1 0 0 5 10 15 20 headroom vo lt age (v) output current (ma) 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 10067-067 figure 30 . dc -to- dc converter headroom vs. output current (see figure 55 ) 0 ?120 ?100 ?80 ?60 ?40 ?20 10 100 1k 10k 100k 1m 10m i out_x psrr (db) frequenc y (hz) av dd = 15v v boost_x = 15v t a = 25c 10067-068 figure 31 . i out_x psrr vs. frequency
data sheet ad5737 rev. b | page 17 of 44 dc- to - dc converter 90 85 80 75 70 65 60 55 50 0 24 20 16 12 8 4 v boost_x efficienc y (%) output current (ma) 0m a t o 24m a range 1k? load external r set f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c av cc = 4.5v av cc = 5v av cc = 5.5v 10067-016 figure 32 . efficiency at v boost_x vs. output current (see figure 55 ) 90 85 80 75 70 65 60 55 50 ?40 100 40 60 80 20 0 ?20 v boost_x efficienc y (%) tempera ture (c) 0m a t o 24m a range 1k? load external r set av cc = 5v f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 20m a output 10067-017 figure 33 . efficiency at v boost_x vs. temperature (see figure 55 ) 80 70 60 50 40 30 20 0 24 20 16 12 8 4 i out_x efficienc y (%) output current (ma) 0m a t o 24m a range 1k? load external r set f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c av cc = 4.5v av cc = 5v av cc = 5.5v 10067-018 figure 34 . output efficiency vs. output current (see figure 55 ) 80 70 60 50 40 30 20 ?40 100 40 60 80 20 0 ?20 i out_x efficienc y (%) tempera ture (c) 0m a t o 24m a range 1k? load external r set av cc = 5v f sw = 410khz induc t or = 10h (xal4040-103) 20m a output 10067-019 figure 35 . output efficiency vs. temperature (see figure 55 ) 0 0.1 0.2 0.3 0.4 0.5 0.6 ?40 ?20 0 20 40 60 80 100 switch resis t ance (?) tempera ture (c) 10067-123 figure 36 . switch resistance vs. temperature
ad5737 data sheet rev. b | page 18 of 44 reference 16 14 12 10 8 6 4 2 0 ?2 0 0.2 0.4 0.6 0.8 1.0 1.2 volt age (v) time (ms) av dd refout t a = 25c 10067-010 figure 37 . refout voltage turn - on transient 4 3 2 1 0 ?1 ?2 ?3 0 2 4 6 8 10 volt age (v) time (s) av dd = 15v t a = 25c 10067-0 11 figure 38 . refout output noise (0.1 hz to 10 hz bandwidth) 150 100 50 0 ?50 ?100 ?150 0 5 10 15 20 time (ms) av dd = 15v t a = 25c volt age (v) 10067-012 figure 39 . refout o utput noise (100 khz bandwidth) 5.0000 5.0005 5.0010 5.0015 5.0020 5.0025 5.0030 5.0035 5.0040 5.0045 5.0050 ?40 ?20 0 20 40 60 80 100 reference output vo lt age (v) tempera ture (c) 30 devices shown av dd = 15v 10067-163 figure 40 . refout voltage vs. temp erature ( when the ad5737 is soldered onto a pcb, the reference shifts due to thermal shock on the package. the average output voltage shift is ?4 mv. measurement of these parts after seven days shows that the outputs typically shift back 2 mv toward their initial values. this second shift is due to the relaxation of stress incurred during soldering.) 5.002 5.001 5.000 4.999 4.998 4.997 4.996 4.995 0 2 4 6 8 10 reference output vo lt age (v) load current (ma) av dd = 15v t a = 25c 10067-014 figure 41 . refout voltage vs. load current 5.00000 4.99995 4.99990 4.99980 4.99985 4.99975 4.99970 4.99965 4.99960 10 15 20 25 30 reference output vo lt age (v) av dd (v) t a = 25c 10067-015 figure 42 . refout voltage vs. av dd
data sheet ad5737 rev. b | page 19 of 44 general 450 400 350 300 250 200 150 100 50 0 0 1 2 3 4 5 di cc (a) sdin vo lt age (v) dv dd = 5v t a = 25c 10067-007 figure 43 . di cc vs. logic input voltage 8 7 0 1 2 3 4 5 6 current (ma) volt age (v) ai dd t a = 25c i out = 0m a 10 15 20 25 30 10067-009 figure 44 . supply current (ai dd ) vs. supply voltage (av dd ) 13.4 13.3 13.2 13.1 13.0 12.9 12.8 12.7 12.6 ?40 ?20 0 20 40 60 80 100 frequenc y (mhz) tempera ture (c) dv dd = 5.5v 10067-020 figure 45 . internal oscillator frequency vs. temperature 14.4 14.2 14.0 13.8 13.6 13.4 13.2 13.0 2.5 3.0 3.5 4.0 4. 5 5.0 5.5 frequenc y (mhz) volt age (v) t a = 25c 10067-021 figure 46 . internal oscillator frequency vs. dv dd supply voltage
ad5737 data sheet rev. b | page 20 of 44 terminology relative accuracy or integ ral nonlinearity (inl) relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation from the best fit line through the dac transfer function. inl is expressed in percent of full - scale range (% fsr). a t ypical inl vs. code plot is shown in figure 8 . differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified dnl of 1 lsb maximum ensur es monotonicity. the ad5737 is guaranteed monotonic by design. a typical dnl vs. code plot is shown in figure 9 . monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5737 is monotonic over its full operating temperature range. offset error o ffset error is the deviation of the analog output from the ideal zero - scale output whe n all dac registers are loaded with 0x0000. it is expressed in % fsr. offset error drift or offset tc offset error drift, or offset tc, is a measure of the change in offset error with changes in temperature and is expressed in ppm fsr/c. gain error gain e rror is a measure of the span er ror of the dac. it is the devia tion in slope of the dac transfer function from the ideal, expressed in % fsr. gain temperature coefficient (tc) gain tc is a measure of the change in gain err or with changes in temperature and is expressed in ppm fsr/c. full - scale error full - scale error is a measure of the output error when full - scale code is loaded to the dac register. ideally, the output should be full - scale ? 1 lsb. full - scale error is expressed in % fsr. full - scale tempera ture coefficient (tc) full - scale tc is a measure of the change in full - scale error with changes in temperature and is expressed in ppm fsr/c. total unadjusted error (tue) total unadjusted error (tue) is a measure of the output error t hat includes all the error measurements: inl error, offset error, gain error, temperature, and t ime. tue is expressed in % fsr. dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full- scale output change on one dac while monitoring another dac, which is at midscale. current loop compliance voltage the c urrent l oop c ompliance v oltage is t he maximum voltage at the i out _x pin for which the output current is equal to the programmed value. voltage reference thermal hysteresis voltage reference thermal hysteresis is the difference in output voltage measured at +25c compared to the output voltage measured at +25c after cycling the temperature from + 25c to ?40c to +105c and back to +25c. the hysteresis is specified for the first and second temperature cycles and is expressed in ppm. power - on glitch energy power - on glitch energy is the impulse injected into the analog output when the ad5737 is powered on. it is specified as the area of the glitch in nv - sec (see figure 23 ). power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the po wer supply voltage. reference temperature coefficient (tc) reference tc is a measure of the change in the reference output voltage with change s in temperature. it is expressed in ppm/c. line regulation line regulation is the change in the reference output voltage due to a specified change in supply voltage. it is expressed in ppm/v. load regulation load regulation is the change in the reference output voltage due to a specified change in load current. it is expressed in ppm/ma. dc -to - dc converter headroom dc - to - dc c onverter h eadroom is the difference between the voltage required at the current output and the voltage supplied by the dc - to - dc converter (s ee figure 30). output efficiency o utput efficiency is defined a s the ratio of the power delivered to a channels load and the power delivered to the channels dc - to - dc input. the v boost_ x quiescent current is considered part of the dc - to - dc converters losses. cc cc load out aiav ri 2 efficiency at v boost_x the efficie ncy at v boost_ x is defined as the ratio of the power delivered to a channels v boost_x supply and the power delivered to the channels dc - to - dc input. the v boost_x quiescent current is considered part of the dc - to - dc converters losses . cc cc xboost out aiav vi _
data sheet ad5737 rev. b | page 21 of 44 theory of operation the ad5737 is a quad, precision digital - to - current loop converter designed to meet the requirements of industrial process control applications. it provides a high precision, fully inte grated, low cost, single- chip solution for generating current loop outputs. the current ranges available are 0 ma to 20 ma, 4 ma to 20 ma , and 0 ma to 24 ma . t he output configuration is user - selectable via the dac control register. on- chip dynamic power co ntrol minimizes package power dissipation (see the dynamic power control section) . dac architecture the dac core architecture of the ad5737 consists of two matched dac se ctions. a simplified circuit diagram is shown in figure 47 . the four msbs of the 12 - bit data - word are decoded to drive 15 switches, e1 to e15. each switch connects one of 15 matched resistors either to ground or to the reference buffer output. the remaining eight bits of the data - word drive switch s0 to switch s7 of a n 8- bit voltage mode r - 2r ladder network. 8-bit r-2r ladder four msbs decoded in to 15 equa l segments 2r 2r s0 s1 s7 e1 e2 e15 v out 2r 2r 2r 2r 2r 10067-069 figure 47 . dac ladder structure the voltage output from the dac core is c onvert ed to a current, which is then mirrored to the supply rail so that the application sees only a current source output (see figure 48 ) . the current outputs are supplied by v boost_x . 12-bit dac v boost_x r2 t2 t1 r3 i out_x r set a1 a2 10067-071 figure 48 . voltage -to- current conversion circuitry reference buffers the ad5737 can operate with either an external or internal reference. the reference input requires a 5 v reference for specified performance. this in put voltage is then buffered before it is applied to the dac. power - on state of the ad5737 when the ad5737 is first powered on, the i out_x pins are in tristate mode . a fter a device power - on or a device reset, it is recommended that the user wait at least 100 s before writing to the device to allow time for internal calibrations to take place. serial interface the ad5737 is co ntrolled by a versatile 3 - wire serial interface that operates at clock rates of up to 30 mhz and is compatible with spi, qspi, microwire, and dsp standards. data co ding is always straight binary. input shift register the input shift register is 24 bits wid e. data is loaded into the device msb first as a 24 - bit word under the control of the serial clock input, sclk. data is clocked in on the falling edge of sclk. if packet error checking ( pec ) is enabled, an additional eight bits must be written to the ad5737 , creating a 32 - bit serial interface (see the packet error checking section) . t he dac outputs can be updated in one of two ways : individual dac updating or simultaneous updating of all dacs. individual dac updating to up d ate an individual dac , ldac is held low while data is clocked into the dac data register. the addressed dac output is updated on the rising edge of sync . see table 3 and figure 3 for timing information. simultaneous updating of all dacs to update all dacs simultaneously , ldac is held high while data is clocked into the dac data register. after ldac is taken high, o nly the first write to the dac data register of each channel is valid ; s ubsequent writes to the dac data register are ignored , al though the se subsequent writes are returned if a readback is initiated . all dac outputs are updated by taking ldac low after sync is taken high. i out_x dac register inter f ace logic output amplifiers ldac sdo sdin 12-bit dac v refin sync dac d at a register offset and gain calibr a tion dac input register sclk 10067-072 figure 49 . simplified serial interface of the input loading circuitry for one dac channel
ad5737 data sheet rev. b | page 22 of 44 transfer function for t he 0 ma to 20 ma, 0 ma to 24 ma, and 4 ma to 20 ma current output ranges, the output current is expressed by the following equations: for the 0 ma to 20 ma range d i n out ? ? ? ? ? ? ? ? = 2 ma20 for the 0 ma to 24 ma range d i n out ? ? ? ? ? ? ? ? = 2 ma24 for the 4 ma to 20 ma range ma4 2 ma16 + ? ? ? ? ? ? ? ? = d i n out where: d is the decimal equivalent of the code loaded to the dac. n is the bit resolution of the dac.
data sheet ad5737 rev. b | page 23 of 44 registers table 7 , table 8 , and table 9 provide an overview of the registers for the ad5737 . table 7 . data registers for the ad5737 register description dac data registers the four dac data registers (one register per dac channel) are u sed to write a dac code to each dac channel. the dac data bits are d15 to d4. gain registers the four gain registers (one register per dac channel) are used to program the gain trim on a per -c hannel basis. the gain data bits are d15 to d4. offset registers the four offset registers (one register per dac channel) are used to program the offset trim on a per - channel basis . the offset data bits are d15 to d4. clear code registers the four clear code registers (one register per dac channel) are used to program the clear code on a per - channel basis. the clear code data bits are d15 to d4. table 8 . c ontrol registers for the a d5737 register description main control register the main control register is used to configure functions for the entire part. these functions include the following: enabling status readback during a write; enabling the output on all four dac channels si multa - neously; power - on of the dc -to - dc converter on all four dac channels simultaneously; and enabling and configuring the watchdog timer. for more information, see the main control register s ection. dac control registers the four dac control registers (one register per dac channel) are used to configure the following functions on a per - channel basis: output range (for example, 4 ma to 20 ma); selection of the internal current sense resistor or an external current sense resistor; enabling/disabling the use of a clear code; enabling/disabling the internal circuitry (dc - to - dc converter, dac, and internal amplifiers); power - on/power - off of the dc - to -dc converter; and enabling/disabling the output channel. software register the softw are register is used to perform a reset , to toggle the user bit in the status register , and, as part of the watchdog timer feature, to verify correct data communication operation. dc -to - dc control register the dc -to - dc control register is used to set the control parameters for the dc -to - dc converter: maximum output voltage, phase, and switching frequency. this register is also used to select the internal compensa - tion resistor or an external compensation resistor for the dc - to - dc converter. slew rate cont rol registers the four slew rate control registers (one register per dac channel) are used to program the slew rate of the dac output. table 9 . readback register for the ad5737 register description status register the status register contains any fault information, as well as a user toggle bit.
ad5737 data sheet rev. b | page 24 of 44 enabling the output to correctly write to and set up the part from a power - on conditi on, use the following sequence: 1. perform a hardware or softwar e reset after initial power - on. 2. configure the dc - to - dc converter supply block. set the dc - to - dc switching frequency, the maximum output voltage allowed, and the dc - to - dc converter phase between channels. 3. configure the dac control register on a per - channel basis. select the output range, and enable the dc - to - dc converter block (dc_dc bit). other control bits can also be config - ured. set the int_enable bit, but do not set the outen (output enable) bit . 4. write the required code to the dac data register . this step implements a full internal dac calibration . for reduced output glitch, allow at least 200 s before performing step 5. 5. write to the dac control register again to enable the output (set the outen bit). f igure 50 provides a flowchart of this sequence. power on. step 1: perform a software/hardware reset. step 4: write to one or more dac data registers. step 2: write to dc-to-dc control register to set dc-to-dc clock frequency, phase, and maximum voltage. step 3: write to dac control register. select the dac channel and output range. set the dc_dc bit and other control step 5: wr ite to dac control register. reload 10067-073 allow at least 200s between step 3 and step 5 for reduced output glitch. bits as required. set the int_enable bit but do not set the outen bit. sequence as in step 3. set the outen bit to enable the output. figure 50 . programming sequence to correctly enable the output reprogramming the output range when changing the range of an output , the same sequence described in the enabling the output section should be used. it is recommended that the range be set to 0 v ( zero scale or midscale) before the output is disabled . because the dc - to - dc switching frequency, maximum output voltage, and phase h ave already been selected, there is no need to reprogram these values . figure 51 provides a flowchart of this sequence. channe l output is enabled. step 3: write v alue t o the dac d at a register. step 1: write t o channe l ?s dac d at a register. set the output t o 0v (zero or midscale). step 2: write t o dac contro l register. disable the output (outen = 0) and step 4: write t o dac contro l register. reload sequence as in ste p 2. 10067-074 set the new output range. kee p the dc_dc bit and the int_enable bit se t. set the outen bit t o enable the outpu t. figure 51 . programming sequence to change the output range
data sheet ad5737 rev. b | page 25 of 44 data registers the input shift register is 24 bits wide. when pec is enabled, the input shift register is 32 bits wide, with the last eight bits correspond ing to the pec code (see the packet error checking section for more information about pec). when writing to a data register, the format shown in table 10 must be used. dac data register when writing to a dac data register, bit d15 to bit d4 are the dac data bits. table 12 shows the register format, and table 11 describes the function s of bit d23 to bit d16. table 10. input shift register for a write operation to a data register msb lsb d23 d2 2 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 data table 11. descriptions of data register bits[d23:d16] bit name description r/ w this bit i ndicates whether the addressed register is written to or read from . 0 = write to the addressed register. 1 = read from the addressed register. dut_ad1, dut_ad0 used in association with the external pins ad1 and ad0, these bits determine which ad5737 device is being addressed by the system controller. dut_ad1 dut_ad0 part addressed 0 0 pin ad1 = 0, pin ad0 = 0 0 1 pin ad1 = 0, pin ad0 = 1 1 0 pin ad1 = 1, pin ad0 = 0 1 1 pin ad1 = 1, pin ad0 = 1 dreg2 , dreg1, dreg0 these bits select the register to be written to. if a control register is selected (dreg[2:0] = 111) , the creg bits in the control register select the specific control register to be written to (see table 19). dre g2 dreg1 dreg0 function 0 0 0 write to dac data register ( one dac channel ) 0 0 1 reserved 0 1 0 write to gain register (one dac channel ) 0 1 1 write to gain register s (all dac channel s) 1 0 0 write to offset register (one dac channel ) 1 0 1 wri te to offset register s (all dac channel s) 1 1 0 write to clear code register (one dac channel ) 1 1 1 write to a control register dac_ad1, dac_ad0 these bits are used to specify the dac channel. if a write to the part does not apply to a specific dac c hannel, these bits are dont care bits. dac_ad1 dac_ad0 dac channel 0 0 dac a 0 1 dac b 1 0 dac c 1 1 dac d table 12 . pr ogramming the dac data register d23 d22 d21 d20 d19 d18 d17 d16 d15 to d4 d3 to d0 r/ w dut_ad1 dut_ad0 0 0 0 dac_ad1 dac_ad0 dac data x 1 1 x = dont care.
ad5737 data sheet rev. b | page 26 of 44 gain register the 12 - bit gain register allows the user to adjust the gain of each channel in steps of 1 lsb . to write to the gain register of one dac channel , set the dr eg[2:0] bits to 010 (see table 13). t o write the same gain code to all four dac channels at the same time , set the dreg[2:0] bits to 011. the gain register coding is straight binary , as shown in table 14 . the default code in the gain register is 0xffff. t he maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy (for more information, s ee the d igital offset and gain control section ). offset register the 12 - bit offset register allows the user to adjust the offset of each channel by ?2048 lsb to +2047 lsb in steps of 1 lsb. to write to the offset register of one dac channel , set the dreg[2:0] bits to 100 (see table 15 ). t o write the same offset code to all four dac channels at the same tim e, set the dreg[2:0] bits to 101. the offset register coding is straight binary , as shown in table 16 . the default code in the offset register is 0x8000, which results in zero offset programmed to the output (for m ore infor - mation, s ee the digital offset and gain control section ). clear code register the 12 - bit clear code register allows the user to set the clear value of each channel . to configure a channel to be cleared w hen the clear pin is activated, set the clr_en bit in the dac control register for that channel (see table 23 ). to write to the clear code register, set the dreg[2:0] bits to 110 (see tabl e 17 ). the default clear code is 0x0000 (for more informa - tion, s ee the asynchronous clear section ). table 13 . programming the gain register r/ w dut_ad1 dut_ad0 dr eg2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d4 d3 to d0 0 device address 0 1 0 dac channel address gain adjustment 1 111 table 14. gain register bit descriptions gain adjustment g15 g14 g13 to g5 g4 g3 to g0 +4096 lsb 1 1 111111111 1 1111 +4095 lsb 1 1 111111111 0 1111 1111 1 lsb 0 0 000000000 1 1111 0 lsb 0 0 000000000 0 1111 table 15. programming the offset register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 d1 5 to d4 d3 to d0 0 device address 1 0 0 dac channel address offset adjustment 0 000 table 16 . offset register bit descriptions offset adjustment of15 of14 of13 of12 to of5 of4 of3 to of0 +2047 lsb 1 1 1 11111111 1 0000 +2046 lsb 1 1 1 11111111 0 0000 0000 no adjustment (default) 1 0 0 00000000 0 0000 0000 ?2047 lsb 0 0 0 00000000 1 0000 ?2048 lsb 0 0 0 00000000 0 0000 table 17 . programming the clear code register r/ w dut_ad1 dut_ad0 dreg2 dreg1 dreg0 dac_ad1 dac_ad0 d15 to d4 d3 to d0 0 device address 1 1 0 dac channel address clear code 0 000
data sheet ad5737 rev. b | page 27 of 44 control registers when writing to a control register, the format shown in table 18 must be used. see table 11 for information ab out the configura - tion of bit d23 to bit d16. the control registers are addressed by setting the dreg[2:0] bits (bits[d20:d18] in the input shift register) to 111 and then setting the creg[2:0] bits to select the specific control register (see table 19 ). main control register the main control register options are shown in table 20 and table 21 . see the device features sect ion for more information about the features controlled by the main c ontrol register. table 18. input shift register for a write operation to a control register msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 to d0 r/ w dut_ad1 dut_ad0 1 1 1 dac_ad1 dac_ad0 creg2 creg1 creg0 data table 19. control register addresses (creg [ 2:0] bits ) creg2 (d15) creg1 (d14) creg0 (d13) control register 0 0 0 slew rate control regis ter (one per channel) 0 0 1 main control register 0 1 0 dac control register (one per channel) 0 1 1 dc -to - dc control register 1 0 0 software register table 20. programming the main control register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 to d0 0 0 1 0 statread ewd wd1 wd0 x 1 x 1 outen_all dcdc_all x 1 1 x = dont care. table 21 . main control register bit descriptions bit name description statread enable status readback during a write. see the status readback during a write section. 0 = disable status readback (default). 1 = e nable status readback . ewd enable the watchdog timer. see the watchdog timer section. 0 = d isable the watchdog timer (default). 1 = enable the watchdog timer. wd1, wd0 timeout select bits. used to select the timeout period for the watchdog timer. wd1 wd0 timeout period (ms) 0 0 5 0 1 10 1 0 100 1 1 200 outen_all setting this bit to 1 e nables the output on all four dacs simultaneously. do not use the outen_all bit when using the outen bit in the dac control register. dcdc_all setting this bit to 1 powers up the dc -to - dc converter on al l four channels simultaneously. to power down the dc - to - dc converters, all channel outputs must first be disabled. do not use the dcdc_a ll bit when using the dc_dc bit in the dac control register.
ad5737 data sheet rev. b | page 28 of 44 dac control register the dac control register is used to configure each dac channel. the dac control register options are shown in table 22 and table 23. table 22 . programming the dac control register d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 x 1 x 1 x 1 x 1 int_enable clr_en outen rset dc_dc x 1 r2 r1 r0 1 x = dont care. table 23 . dac control register bit descriptions bit name description int_enable powers up the dc - to - dc converter, dac, and internal amp lifiers for the selected channel. this bit applies to individual channels only; it d oes not enable the ou tput. after setting this bit, i t is recommended that a >200 s delay be observed before enabling the output to reduce the output enable glitch. see figure 24 for plots of this glitch. clr_en per - channel clear enable bit. this bit s pecifies whether the selected channel is clear ed when the clear pin is activated. 0 = channel is not cleared when the part is cleare d (default). 1 = channel is cleared when the part is cleared. outen enables or disables the selected output channel. 0 = c hannel disabled (default). 1 = channel enabled. rset selects the internal current sense resistor or an external current sense resist o r for the selected dac channel. 0 = e xternal resistor selected (default). 1 = i nternal resistor selected . dc_dc powers up or powers down the dc -to - dc converter on the selected channel. all dc - to - dc converters can be powered up simultaneously using the dc dc_all bit in the main control register. to power down the dc -to - dc converter, the outen and int_enable bits must also be set to 0. 0 = dc -to - dc converter is powered down (default). 1 = dc -to - dc converter is powered up. r2, r1, r0 selects th e output range to be enabled. r2 r1 r0 output range selected 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 reserved 1 0 0 4 ma to 20 ma current range 1 0 1 0 ma to 20 ma current range 1 1 0 0 ma to 24 ma current range
data sheet ad5737 rev. b | page 29 of 44 software register the so ftware register allows the user to perform a software reset of the part. this register is also used to set the user toggle bi t, d11, in the status register and as part of the watchdog timer f eature when that feature is enabled. bit d12 in the software regi ster can be used to ensure that communication has not been lost between the mcu and the ad5737 and that the datapath lines are working properly (that is, sdi n , sclk, and sync ). when the wa tchdog timer feature is enabled, the user must write 0x195 to bits[d11: d 0] of the software register within the timeout period. if this command is not received within the timeout period, the alert pin signals a fault condition. this command is only required when the watchdog timer feature is enabled. dc - to - dc control register the dc - to - dc control register allows the user to con figure the dc - to - dc switching frequency and phase, as well as the maximum allowable dc - to - dc output voltage. the dc - to - dc control reg ister options are shown in table 26 and table 27. table 24 . programming the software register d15 d14 d13 d12 d11 to d0 1 0 0 user p rogram reset c ode/spi c ode table 25. software register bit descriptions bit name description user program this bit is mapped to bit d11 of the status register. when this bit is set to 1, bit d11 of the status register is set to 1. w hen this bit is set to 0, bit d11 of the s tatus register is also set to 0 . this feature can be used to ensure that the spi pins are working correctly by writing a known bit value to this register and then reading back bit d11 from the status register. reset code/spi code option description rese t code writing 0x555 to bits[d11:d0] performs a software reset of th e ad5737 . spi code if the watchdog timer feature is enabled, 0x195 must be written to the software register ( bits[d 11: d 0] ) within the programmed timeout period (see table 21 ). table 26. programming the dc -to - dc control register d15 d14 d13 d12 to d7 d6 d5 to d4 d3 to d2 d1 to d0 0 1 1 x 1 dc - dc c omp dc - dc p hase dc - dc f req dc - dc maxv 1 x = don t care. table 27. dc -to - dc control register bit descriptions bit name description dc - dc comp selects the internal compensation resistor or an external compensation resistor for the dc -to - dc converter. see the dc -to - dc converter compensation capacitors section and the ai cc supply requirements slewing section . 0 = selects the internal 150 k? compensation resistor (default). 1 = bypasses the internal compensation resistor. when this bit is set to 1, an external compensation resistor must be used; this resistor is placed at the comp dcdc_x pin in series with the 10 nf dc - to - dc compensation capacitor to ground. typically, a resistor of ~50 k? is recommended. dc - dc phase user - programmable dc -to - dc converter phase (between channels). 00 = all dc -to - dc converters clock on the same edge (default). 01 = channel a and channel b clock on the same edge; channel c and channel d clock on the opposite edge. 10 = channel a and channel c clock on the same edge ; channel b and channel d clock on the opposite edge. 11 = channel a, channel b, channel c, and channel d clock 90 out of phase from each other. dc - dc freq s witching frequency for the dc -to - dc converter ; this frequency is divided down from the internal 13 mhz oscillator (see figure 45 and figure 46 ). 00 = 250 khz 10% . 01 = 410 khz 10% (default). 10 = 650 khz 10%. dc - dc maxv maximum allowed v boost_x volt a ge supplied by the dc - to - dc converter. 00 = 23 v + 1 v/?1.5 v (default). 01 = 24.5 v 1 v. 10 = 27 v 1 v. 11 = 29.5 v 1 v.
ad5737 data sheet rev. b | page 30 of 44 slew rate control regist er this register is used to program the slew rate control for the selected dac channel. the slew rate control is enabled/ disabled and programmed on a per - channel basis. see table 28 and the digital slew rate control section for more information. readback operation readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. see table 29 for the bits associated with a read - back operation. the dut_ad1 and dut_ad0 bits, in association with bits[ rd4: rd 0], select the register to be read (see table 30 ). the remaining data bit s in the write sequence are don t care bits . during the next spi transfer , the data that appears on the sdo output contains the data from the previously addressed register (see figure 4 ) . this second spi transfer should be either a request to read another register o n a third data transfer or a no operation command. the no operation command for dut a ddress 00 is 0x1ce000 ; for other dut addresses, bits[d22:d21] are set accordingly . readback example to read back the gain register of ad5737 device 1, channel a , implement the following sequence: 1. write 0xa80000 to the input register to configure device address 1 for read mode with the gain register of channel a selected. t he data bi ts, d15 to d0, are dont care bit s. 2. execute anoth er read command or a no operation com - mand (0x 3 ce000). during this command, the data from the channel a gain register is clocked out on the sdo line. table 28. programming the slew rate control register d15 d14 d13 d12 d11 to d7 d 6 to d3 d2 to d0 0 0 0 s r e n x 1 sr_clock sr_step 1 x = dont care. table 29 . input shift register for a read operation msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 to d0 r/ w dut_ad1 d ut_ad0 rd4 rd3 rd2 rd1 rd0 x 1 1 x = dont care. table 30 . read address es (bits[rd4:rd0]) rd4 rd3 rd2 rd1 rd0 function 0 0 0 0 0 read dac a data register 0 0 0 0 1 read dac b data register 0 0 0 1 0 read dac c data register 0 0 0 1 1 read dac d data register 0 0 1 0 0 read dac a control register 0 0 1 0 1 read dac b control register 0 0 1 1 0 read dac c control register 0 0 1 1 1 read dac d control register 0 1 0 0 0 read dac a gain register 0 1 0 0 1 read dac b gain regi ster 0 1 0 1 0 read dac c gain register 0 1 0 1 1 read dac d gain register 0 1 1 0 0 read dac a offset register 0 1 1 0 1 read dac b offset register 0 1 1 1 0 read dac c offset register 0 1 1 1 1 read dac d offset register 1 0 0 0 0 read dac a clear code register 1 0 0 0 1 read dac b clear code register 1 0 0 1 0 read dac c clear code register 1 0 0 1 1 read dac d clear code register 1 0 1 0 0 read d ac a slew rate control register 1 0 1 0 1 read dac b slew rate control register 1 0 1 1 0 read d ac c slew rate control register 1 0 1 1 1 read dac d slew rate control register 1 1 0 0 0 read status register 1 1 0 0 1 read main control register 1 1 0 1 0 read dc -to - dc control register
data sheet ad5737 rev. b | page 31 of 44 status register the status register is a read - only register. this register contains any fault information , as a well as a ramp active bit (bit d 9 ) and a user toggle bit (bit d11). when the statread bit in the main control register is set, the status register contents can be read back on the sdo pin during every wri te sequence. alterna - tively, if the statread bit is not set, the status register can be read using the normal readback operation (see the readback operation section) . table 31 . decoding t he status register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dc - dcd dc - dcc dc - dcb dc - dca user t oggle pec e rror ramp a ctive over t emp x 1 x 1 x 1 x 1 i out_d f ault i out_c f ault i out_b f ault i out_a f ault 1 x = dont care. t able 32. status register bit descriptions bit name description dc - dcd t his bit is set if the dc -to - dc converter on channel d cannot maintain compliance , for example, if the dc -to - dc converter is reaching its v max voltage ; i n this c ase, the i out_d fault bit is also set. see the dc -to - dc converter v max functionality section for more information about the operation of this bit under this condition. dc - dcc this bit is set if the dc -to - dc converter on channel c cannot maintain compliance, for example, if the dc -to - dc converter is reaching its v max voltage ; i n this case, the i out_c fault bit is also set. see the dc -to - dc converter v max functionality section for more information about the operation of this bit under this condition. dc - dcb this bit is set if the dc -to - dc converter on channel b cannot maintain compliance , for example, if the dc -to - dc converter is reaching its v max voltage ; i n this case, the i out_b fault bit is also set. see the dc - to - dc converter v max functionality section for more information about the operation of this bit under this condition. dc - dca this bit is set if the dc -to - dc converter on channel a cannot maintain complianc e, for example, if the dc -to - dc converter is reaching its v max voltage ; i n this case, the i out_ a fault bit is also set. see the dc -to - dc converter v max functionality section for more information about the operation of this bit und er this condition. user toggle user toggle bit. this bit is set or cleared via the software register and can be used to verify data communications , if needed. pec error denotes a pec error on the last data - word received over the spi interface. ramp act ive this bit is set while any output channel is slewing ( digital slew rate control is enabled on at least one channel). over t emp this bit is set if the ad5737 core temperature exceeds approximately 150c. i out _d fault this bit is set if a fault is detected on the i out_d pin. i out_c fault this bit is set if a fault is detected on the i out_c pin. i out_b fault this bit is set if a fault is detected on the i out_b pin. i out_a fault this bit is set if a fault is d etected on the i out_a pin.
ad5737 data sheet rev. b | page 32 of 44 device features fault output the ad5737 is equipped with a fault pin, an active low , open - drain output that allows several ad5737 devices to be connected together to one pull - up resistor for global fault detection. the fault pin is forced active by any one of the following fault conditions : ? the voltage at i out_x attempts to rise above the compliance range due to an open - loop circuit or insufficient power supply voltage. the internal circuitry that develops the fault output avoids using a comparator with windowed limits because this requires an actual output error before the fault output be comes active. instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 v of remaining drive capability. thus, the fault output is activated slightly before the compliance limit is reac hed. ? an interface error is detected due to a pec failure (s ee the packet error checking section). ? t he core temperature of the ad5737 exceeds approxi - mately 150c. the i o ut_x fault, pec error, and over t emp bits of the status register are used in conjunction with the fault output to inform the user which fault condition caused the fault output to be activated. digital offset and g ain co ntrol each dac channel has a gain (m) register and an offset (c) register, which allow trimming out of the gain and offset errors of the entire signal chain. data from the dac data register is operated on by a digital multiplier and adder controlled by the contents of the gain and offset registers ; t he calibrated dac data is then st ored in the dac input register (see figure 52 ). dac input register dac dac d at a register gain (m) register offset (c) register 10067-075 figure 52 . digita l offset and gain control although figure 52 indicates a multiplier and adder for each channel, the device has only one multiplier and one adder, which are shared by all four channels. this design has impli - cations for the update speed when several channels are updated at once (see table 3 ). when data is written to the gain (m) or offset (c) register, the output is not automatically updated. instead, the next write to the dac channel uses the new gain and offset values to perform a new calibratio n and automatically updates the channel. the output data from the calibration is routed to the dac input register. this data is then loaded to the dac , as described in the serial interface section. both the gain register and the offset register ha ve 12 bits of resolution. the correct order to calibrate the gain and offset is to first calibrate the gain and then calibrate the offset. the value (in decimal) that is written to the dac input register can be calculated a s follows: 11 12 2 2 )1( ?+ + = c m d code r dacregiste (1) where: d is the code loaded to the dac data register of the dac channel . m is the code in the gain register (default code = 2 12 ? 1). c is the code in the offset register (default code = 2 11 ). status readback during a write the ad5737 can be configured to read back the contents of the status register during every write sequence. this fea ture is enabled using the statread bit in the main control register. when this feature is enabled, the user can continuously monitor the status register and act quickly in the case of a fault. when status readback during a write is enabled, the contents o f the 16 - bit status register (see table 32) are output on the sdo pin, as shown in figure 5 . w hen the ad5737 is power ed up , the status readback during a write feature is disabled . when this feature is enabled, readback of registers other than the status register is not available . to read back any other register, clear the statread bit before following the readback sequence (see the readback operation section) . the statread bit can be set high again after the register read. asynchronous clear clear is an active high, edge sensitive input that allows the output to be cleared to a preprogrammed 1 2- bit code. t his code is user - programmable via a per - channel 1 2- bit clear code register. for a channel to be clear ed , set th e clr_en bit in the dac control register for that channel . if the clear function on a channel is not enabled, the outp ut remains in its current s tate, independent of the level of the clear pin. when the clear signal return s low, the relevant outputs remain cleared u ntil a new value is programmed to them .
data sheet ad5737 rev. b | page 33 of 44 packet error checkin g to verify that data has been received correctly in noisy environ - ments, the ad5737 offers the option of packet error checking based on an 8 - bit cyclic redundancy check (crc - 8) . the device controlling the ad5737 should generate an 8 - bit fra me check sequence using the following polynomial : c ( x ) = x 8 + x 2 + x 1 + 1 this value is added to the end of the data - word, and 32 bits are sent to the ad5737 before sync goes high. if the ad5737 sees a 32- bit frame, it performs the error check when sync goes high. if the error check is valid, the data is written to the selected register. if the error check fails, the fault pin goes low and the pec error bit in the status register is set. after the status register is read , fault returns high (assuming that there are no other faults), and the pec error bit is cleared automatically. sdin sync sclk upd a te on sync high msb d23 lsb d0 24-bit d at a 24-bit d at a transfer?no error checking sdin f au lt sync sclk on ly if error check passed f au l t pin goes low if error check f ails msb d31 lsb d8 d7 d0 24-bit d at a 8-bit crc 32-bit d at a transfer with error checking 10067-180 upd a te on sync high figure 53 . pec timing packet error checking can be used for transmi tt ing and receiv - ing data packets. if status readback during a write is enabled, the pec values returned during the status readback operation should be ignored. if status re adback during a write is disabled, the user can still use the normal readback operation to monitor status register activity with pec. watchdog timer when enabled, an on - chip watchdog timer generates an alert signal if 0x195 is not written to the soft ware register within the programmed timeout period. this feature is useful to ensure that communication has not been lost between the mcu and the ad5737 and that the datapath lines are working properly (that is, sdi n , sclk, and sync ). if 0x195 is not received by the software register within the timeout period, the alert pin signals a fault condition. the alert pin is active high and can be connected directly to the clear pin to enable a clea r in the event that comm unication from the mcu is lost. to enable t he watchdog timer and set the timeout period (5 ms, 10 ms, 100 ms, or 200 ms), program the main control register (see table 20 and table 21 ). alert output the ad5737 is equipped with an alert pin. this pin is an active high cmos output. the ad5737 also has an internal watchdog timer. when enabled, the wa tchdog timer monitors spi communications. if 0x195 is not received by the software register within the timeout per iod, the alert pin is activated. internal reference the ad5737 contains an integrated 5 v voltage reference with initial accuracy of 5 mv maximum and a temperature coefficient of 10 ppm /c maximum. the reference voltage is buffered and is externally available for use elsewhere within the system. external current setting resistor r set is an internal s ense resistor that is part of the voltage - to - current conversion circuitry (see figure 48) . the stability of the output current value over temperature is dependent on the stability of the r set value . to improve the stability of the output current over temperature, the internal r set resistor, r1, can be bypassed and an external , 15 k? , low drift resistor can be connected to the r set_x pin of the ad5737 . the external resistor is selected via the dac control register (see table 23). table 1 provides the performance specifications for the ad5737 with both the internal r set resistor and an external, 15 k? r set resistor. the use of an external r set resistor allows for improved perf ormance over the internal r set resistor option. the external r set resistor specification s assume an ideal resistor; the actual performance depends on the absolute value and temperature coefficient of the resistor used. this directly affects the gain error of the output and , thus , the total unadjusted error. to arrive at the gain/tue error of the output with a specific external r set resistor, add the absolute error percentage of the r set resistor directly to the gain/tue err or of the ad5737 with the exter nal r set resistor, as shown in table 1 (expressed in % fsr).
ad5737 data sheet rev. b | page 34 of 44 hart connectivity the ad5737 has four chart pins, one correspo nding to each output channel. a hart signal can be coupled into these pins. the hart signal appears on the corresponding current output, if the output is enabled. table 33 shows the recommended input voltages for the hart signal a t the chart pin. if these voltages are used, the current output should meet the hart amplitude specifications. table 33 . chart input voltage to hart output current r set chart input voltage current output (hart) internal r set 150 mv p-p 1 ma p -p external r set 170 mv p -p 1 ma p -p figure 54 shows the recommended circuit for attenuating and coupling the hart signal. a minimum capacitance of c1 + c2 is required to ensure that the 1.2 khz and 2.2 khz hart frequencies are not significantly attenuated at the output. the re commended values are c1 = 22 nf and c2 = 47 nf. hart modem output c1 c2 chartx 10067-076 figure 54 . coupling the hart signal digitally controlling the slew rate of the output is necessary to me et the analog rate of change requirements for hart. digital slew rate co ntrol the digital slew rate control feature of the ad5737 allows the user to control the rate at which the output value changes. with the sl ew rate control feature disabled, the output value changes at a rate limited by the output drive circuitry and the attached load. to reduce the slew rate, the user can enabl e the digital slew rate control feature using the sren bit of the slew rate control register (see table 28 ). when slew rate control is enabled, the output, instead of slewing directly between two values, steps digitally at a rate defined by the sr_clock and sr_step parameters . these parameters ar e accessible via the slew rate control register (see table 28 ). ? sr_clock defines the rate at which the digital slew is updated ; for example, i f the selected update rate is 8 khz, the output is u pdated every 125 s. ? sr_step defines by how much the output value changes at each update. together, these parameters define the rate of change of the output value. table 34 and table 35 lis t the range of values for the sr_clock and sr_step parameters , respectively . table 34 . slew rate update clock options sr_clock update clock frequency 1 0000 64 k hz 0001 32 khz 0010 16 khz 0011 8 khz 0100 4 khz 0101 2 khz 0 110 1 khz 0111 500 hz 1000 250 hz 1001 125 hz 1010 64 hz 1011 32 hz 1100 16 hz 1101 8 hz 1110 4 hz 1111 0.5 hz 1 these clock frequencies are divided down from the 13 mhz internal oscillator (s ee table 1 , figure 45 , and figure 46). table 35 . slew rate step size options sr_step step size ( lsb ) 000 1 001 2 010 4 011 16 100 32 101 64 110 128 111 256 the following equation describes the slew rate as a function of the step size, the update clock frequency, and the lsb size. size lsb frequency clock update size step change output rate slew = where: slew rat e is expressed in seconds. output change is expressed in amp ere s. the update clock f requency for any given value is the same for all output ranges. the step size, however, varies across output ranges for a given value of step size because the lsb size is different for each output range.
data sheet ad5737 rev. b | page 35 of 44 when the slew rate control feature is enabled, all output changes occur at the programmed slew rate (see the dc - to - dc converter settling time section for more information). for example, if the clear pin is asserted, the output slews to the clear value at the programmed slew rate (assuming that the channel is enabled to be cleared). if more than one channel i s enabled for digital slew rate control, care must be taken when asserting the clear pin. if a channel under slew rate control is slewing when the clear p in is asserted, other channels under slew rate control may change directly to their clear code not under slew rate control. dynamic power c ontrol t he ad5737 provides integrated dynamic power control using a dc - to - dc boost converter circuit. this circuit reduces power consumption compared with standard designs. in standard current input module designs, the load resistor values can range from typically 50 ? to 750 ?. output module systems must source enough voltage to meet the compliance voltage requirement across the full range of load resistor values. for example, in a 4 ma to 20 ma loop when driving 20 ma, a compliance voltage of >15 v is required. when driving 20 ma into a 50 ? load, a compliance voltage of only 1 v is required. the ad5737 circuitry senses the output voltage and regulates this voltage to meet the compliance requirements plus a small headroom voltage. the ad5737 is capable of driving up to 24 ma through a 1 k? load. dc- to - dc converters the ad5737 contains four independent dc - to - dc converters. these are used to provide dynamic control of the v boost _x supply voltage for each channel (see figure 48 ). figure 55 shows the discre te components needed for the dc - to - dc circuitry, and the following sections describe component selection and operation of this circuitry. av cc l dcdc d dcdc c dcdc 4.7f c fi l ter 0.1f r fi l ter c in sw x v boost_x 10f 10? 10h 10067-077 figure 55 . dc -to- dc circuit table 36 . recommended components for a dc - to - dc converter symbol component value manufacturer l dcdc xal4040 - 103 10 h coilcraft ? c dcdc grm32er71h475ka88l 4 .7 f murata d dcdc pmeg3010bea 0.2 85 v f nxp it is recommended that a 10 ?, 100 nf low - pass rc filter be placed after c dcdc . this filter consumes a small amount of power but reduces the amount of ripple on the v boost_x supply. dc - to - dc converter operati on the on - board dc - to - dc converters use a constant frequency, peak current mode control scheme to step up an av cc input of 4.5 v to 5.5 v to drive the ad5737 output channel. these converters are designed to opera te in discontinuous conduction mode with a duty cycle of <90% typical. discontinuous conduction mode refers to a mode of operation where the inductor current goes to zero for an appreciable percentage of the switching cycle. the dc - to - dc converters are non synchronous ; that is, they require an external schottky diode. dc - to - dc converter output voltage when a channel current output is enabled, the converter regulates the v boost_x supply to 7.4 v (5%) or ( i out r load + he adroom), whichever is greater (see figure 30 for a plot of headroom supplied vs. output current). when the output is disabled, the converter regulates the v boost_x supply to 7.4 v (5%). dc - to - dc converter settling time t he settling time for a step greater than ~1 v (i out r load ) is dominated by the settling time of the dc - to - dc converter. the exception to this is when the required voltage at the i out_x pin plus the compliance voltage is below 7.4 v (5%). fi gure 25 shows a typical plot of the output settling time. this plot is for a 1 k? load. the settling time for smaller loads is faster. the settling time for current steps less than 24 ma is also faster. dc - to - dc converter v max functionality the maximum v boost_x voltage is set in the dc - to - dc control register (23 v, 24.5 v, 27 v, or 29.5 v; see table 27 ). when the maximum voltage is reached, the dc - to - dc converter is disabled, and the v boost_x volt age is allowed to decay by ~0.4 v. after the v boost_x voltage decay s by ~0.4 v, the dc - to - dc converter is reen abled, and the voltage ramps up again to v max , if still required. this operation is shown in figure 56 . 28.6 28.7 28.8 28.9 29.0 29.1 29.2 29.3 29.4 29.5 29.6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v boost_x vo lt age (mv) time (ms) v max 0m a t o 24m a range, 24m a output output unloaded dc-dc maxv bits = 29.5v dc-dcx bit dc-dcx bit = 0 dc-dcx bit = 1 f sw = 410khz t a = 25c 10067-183 figure 56 . operation on reaching v max as shown in figure 56 , the dc - dcx bit in the status register is assert ed when the ad5737 ramps up to the v max value but is deasserted when the voltage decays to v max ? ~0.4 v.
ad5737 data sheet rev. b | page 36 of 44 dc - to - dc converter on - board switch t he ad5737 contains a 0.425 ? internal switch. the switch cur rent is monitored on a pulse - by - pu lse basis and is limited to 0.8 a peak current. dc - to - dc converter switching frequency and phase the ad5737 dc - to - dc converter switching frequency can be selected from the dc - to - dc control register (see table 27) . the phasing of the channels can also be adjusted so that the dc - to - dc con verter s can clock on different edges. for typical applications, a 410 khz frequency is recommended. at light loads (low output current and small load resistor), the dc - to - dc converter enters a pulse - skipping mode to minimize switching power dissipation. dc - to - dc converter inductor selection for typical 4 ma to 20 ma applications, a 10 h inductor (such as the xal4040 - 103 from coi lcraft), combined with a switch ing frequency of 410 khz, allows up to 24 ma to be driven into a load resistance of up to 1 k? with an av cc supply of 4.5 v to 5.5 v. it is important to ensure that the inductor can handle the peak current without saturating, especially at the maximum ambient temperature. if the inductor enters saturation mode, efficiency decreases . the inductance value also drops during saturation and may result in the dc - to - dc converter circuit not being able to supply the required output power. dc - to - dc converter external schottky diode selection the ad5737 requires an exter nal schottky diode for correct opera tion. ensure that the schottky diode is rated to handle the maximum reverse breakdown voltage expected in operation and that the maximum junction temperature of the diode is not exceeded. the average current of the diode is approximately equal to the i load current. diodes with larger forward voltage drops result in a decrease in efficiency. dc - to - dc converter compensation capacitors because the dc - to - dc converter operates in discontinuous conduc - tion mode, the uncompensat ed transfer function is essentially a single- pole transfer function. the pole frequency of the transfer function is determined by the output capacitance, input and output voltage, and output load of the dc - to - dc converter. the ad5737 uses an external capacitor in conjunction with an internal 150 k? resistor to compensate the regulator loop. alternatively, an external compensation resistor can be used in series with the compensation capacitor by setting the dc - dc c omp bit in the dc - to -d c control register (see table 27) . in this case, a resistor of ~50 k? is recommended. t he advantages of this configuration are described in the ai cc supply requirements slewing section. for typical applic ations, a 10 nf dc - to - dc com - pensation capacitor is recommended. dc - to - dc converter input and output capacitor selection the output capacitor affects the ripple voltage of the dc - to - dc converter and indirectly limits the maximum slew rate at which the ch annel output current can rise. the ripple voltage is caused by a combination of the capacitance and the equivalent series resistance (esr) of the capacitor. for typical applications , a ceramic capacitor of 4.7 f is recommended . larger capacitors or parall el capacitors improve the ripple at the expense of reduced slew rate. larger capacitors also affect the current requirements of the a v cc suppl y while slewing (see the ai cc supply requirements slewing section ). the capacitance at the output of the dc - to - dc converter should be >3 f under all operating conditions. the input capacitor provides much of the dynamic current required for the dc - to - dc converter and should be a low esr component. for the ad5737 , a low esr tantalum or ceramic capacitor of 10 f is recommended for typical applications. ceramic capacitors must be chosen carefully because they can exhibit a large sensitivity to dc bias voltages and temperature. x5r or x7r dielectrics are preferred because these capacitors remain stable over wider operating voltage and temperature ranges. care must be taken if selecting a tantalum capacitor to ensure a low esr value. ai cc supply requirements static the dc - to - dc converter is designed to supply a v boost _x voltage of v boost_x = i out r load + headroom (2) see figure 30 for a plot of headroom supplied vs. output current . therefore , for a fixed load and output voltage, the output current of the dc - to - dc converter can be calculated by the following formula: cc v boost out cc cc av vi av efficiency out power ai boost = = (3) where: i out is the output current from i out_x in amp ere s. v boost is the efficiency at v boost_x as a fraction (see figure 32 and figure 33).
data sheet ad5737 rev. b | page 37 of 44 ai cc supply requirements slewing the ai cc current requirement while slewing is greater than in static operation because the output power increases to charge the output capacitance of the dc - to - dc converter. this transient current can be quite large (see figure 57 ), although the methods desc ribed in the reducing ai cc current requirements section can reduce the requirements on the av cc supply. if not enough ai cc current can be provided, the av cc voltage drops. due to this av cc drop, the ai cc current required for slewi ng increases further, causing the voltage at av cc to drop further (see equation 3). in this case, the v boost _x voltage and, therefore, the output voltage, may never reach their intended values. because the av cc voltage is common to all channels, this volt age drop may also affect other channels. 0 5 10 15 20 25 30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.5 1.0 1.5 2.0 2.5 i out_x current (m a)/ v boost_x vo lt age (v) ai cc current (a) time (ms) ai cc i out v boost 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 10067-184 figure 57 . ai cc current vs. time for 24 ma step through 1 k? load with internal compensation resistor reducing ai cc current requirements two main methods can be used to reduce the ai cc current requirements. one method is to add an external compensation resistor, and the other is to use slew rate contro l. these methods can be used together. adding an external compensation resistor a compensation resistor can be placed at the comp dcdc_x pin in series with the 10 nf compensation capacitor. a 51 k? exter - nal compensation resistor is recommended. this compensation increases the slew time of the current output but reduces the ai cc transient current requirements. figure 58 shows a plot of ai cc current for a 24 ma step through a 1 k? load when using a 51 k? compensation resistor. the compensation resistor reduces the current requirements through smaller loads even further, as shown in figure 59 . 0 4 12 8 16 24 20 28 32 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 0 0.5 1.0 1.5 2.0 2.5 i out_x current (m a)/ v boost_x vo lt age (v) time (ms) ai cc i out v boost 10067-185 figure 58 . ai cc current vs. time for 24 ma step through 1 k? load with external 51 k? compensation resistor 0 0.1 0.2 0. 3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0m a t o 24m a range 500? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 0 4 12 8 16 24 20 28 32 0 0.5 1.0 1.5 2.0 2. 5 i out_x current (m a)/ v boost_x vo lt age (v) time (ms) ai cc i out v boost 10067-186 figure 59 . ai cc current vs. time for 24 ma step through 500 ? load with external 51 k? compensation resistor
ad5737 data sheet rev. b | page 38 of 44 using slew rate control using slew rate cont rol can greatly reduce the current require - ments of the av cc supply , as shown in figure 60 . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ai cc current (a) 0m a t o 24m a range 1k? load f sw = 410khz induc t or = 10h (xal4040-103) t a = 25c 0 4 12 8 16 24 20 28 32 0 1 2 3 4 5 6 i out_x current (m a)/ v boost_x vo lt age (v) time (ms) ai cc i out v boost 10067-187 figure 60 . ai cc current vs. time for 24 ma step through 1 k? load with slew rate control whe n using slew rate control, it is important to remember that the output cannot slew faster than the dc - to - dc converter. the dc - to - dc converter slews slowest at higher currents through large loads (for example, 1 k?). the slew rate is also dependent on the c onfiguration of the dc - to - dc converter . two examples of the dc - to - dc converter output slew are shown in figure 58 and figure 59. (v boost corresponds to the output voltage of the dc - to - dc converter.) external pmos m ode the ad5737 can also be used with an external pmos transistor per channel, as shown in figure 61 . this mode can be used to limit the on - chip power dissipation of the ad5737 , al though this mode does not reduce the power dissipation of the total system. the igate x functionality is not typically required when using the dynamic pow er control feature ; therefore, figure 61 shows the configuration of the device for a fixed v boost_ x supply. in this configuration , the sw x pin is left floating , and the gnd sw x pin is grounded. the v boost_x pin is conne cted to a minimum supply of 7. 4 v and a maximum supply of 33 v. this supply can be sized according to the maximum load required to be driven. the igatex functionality works by holding the gate of the external pmos transistor at ( v boost_x ? 5 v). this means that the majority of the channel s power dissipation take s place in th e external pmos t ransistor. the external pmos transistor should be selected to to lerate a v ds voltage of at least the v boost_x voltage, as well as to handle the power dissipation r equired. th e external pmos transistor typically has minimal effect on the current output performance. 10067-190 r1 r2 r3 r set_ a r load gndsw a v boost_ a (v boost_a ? 5v) sw a char ta ig a te a current output dac channe l a (left flo a ting) i out_ a dac a 5.0v av cc figure 61 . configuration of c hannel a u sing i gate x
data sheet ad5737 rev. b | page 39 of 44 applications informa tion current output mode with internal r set whe n using the internal r set resistor, the current output is significantly affected by how many other channels using the internal r set are enabled and by the dc crosstalk from these channels. the internal r set specifications in table 1 are for all four channels enabled with the internal r set selected and outputting the same code. for every channel enabled with the internal r set , the offset error decreases. for example, with one current output enabled using the interna l r set , the offset error is 0.075% fsr. this value decreases proportionally as more current channels are enabled; the offset error is 0.056% fsr on each of two channels, 0.029% fsr on each of three channels, and 0.01% fsr on each of four channels. similarl y, the dc crosstalk when using the internal r set is propor - tional to the number of current output channels enabled with the internal r set . for example, with the measured channel at 0x8000 and another channel going from zero to full scale, the dc crosstalk is ?0.011% fsr. with two other channels going from zero to full scale, the dc crosstalk is ?0.019% fsr, and with all three other channels going from zero to full scale, it is ?0.025% fsr. for the full - scale error measurement in table 1 , all channels are at 0xffff. this means that as any channel goes to zero scale, the full - scale error increases due to the dc crosstalk. for example, with the measured channel at 0xffff and three channels at zero scale, the full - scale error is 0.025% fsr . similarly, if only one channel is enabled with the internal r set , the full - scale error is 0.025% fsr + 0.075% fsr = 0.1% fsr. precision voltage re ference selection to achieve the optimum performance from the ad5737 over its full operating temperature range, a precision voltage reference must be used. care should be taken with the selection of the precision voltage reference. the voltage applied to the reference inputs is used to provide a buf fered reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the ad5737 . f our possible sources of error must be consider ed when choosing a voltage reference f or high accuracy applications: initial accuracy, long - term drift, temperature coefficient of the output voltage , and output voltage noise. initial accuracy error on the outp ut voltage of an external ref - er ence can lead to a full - scale error in the dac. the refore, to minimize these errors, a reference with a low initial accuracy error specification is preferred. choosing a reference with an output trim adjustment, such as the adr435 , allows a system designer to tri m out system errors by setting the reference voltage to a voltage other than the nominal. the trim adjust - ment can be used at any temperature to trim out any error. long - term drift is a measure of how much the reference output voltage drifts over time. a r eference with a tight long - term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. the temperature coefficient of the reference output voltage affects inl, dnl, and tue. a reference with a tight temperature coef - ficient specification should be chosen to reduce the dependence of the dac output voltage on ambient temperature. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise must be considered. choos - i ng a reference with as low an output noise voltage as practical for the system resolution required is important. precision voltage references such as the adr435 (xfet ? design) produce low output noise in the 0. 1 hz to 10 hz bandwidth . however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimize the output noise. driving inductive lo ads when driving inductive or poorly defined loads, a capacitor may be required be tween the i out_x pin and the agnd pin to ensure stability. a 0.01 f capacitor between i out_x and agnd ensures stability of a load of 50 mh. the capacitive component of the load may cause slower settling, although this may be masked by the settling time of the ad5737 . there is no maxi - mum capacitance limit for the current output of the ad5737 . table 37 . recommended precision voltage references part no. initial accuracy (mv maximum) long - term drift (ppm typical) temperature coefficient (ppm/c maximum) 0.1 hz to 10 hz noise (v p - p typical) adr445 2 50 3 2.25 adr02 3 50 3 10 adr435 2 40 3 8 adr395 5 50 9 8 ad586 2.5 15 10 4
ad5737 data sheet rev. b | page 40 of 44 transient voltage pr otection the ad5737 contains esd protection diodes that prevent dam - age from normal handling. the industrial control environment can, however, subject i/o circuits to much higher transients. to protect the ad5737 from excessively high voltage transients, external power diodes and a surge current limiting resistor (r p ) are required, as shown in figure 62 . a typical value for r p is 10 ?. t he two protection diodes and the resistor (r p ) must have appro - priate power ratings. r load r d1 d2 p ad5737 v boost_x i out_x agnd c dcdc 4.7f c filter 0.1f r filter 10 ? (from dc- t o-dc converter) 10067-079 figure 62 . output transient voltage protection further protection can be provided using transient voltage sup pressors (tvs s ), also referred to a s transorbs . t hese compo - nents are available as unidirectional suppressors, which protect against positive high voltage transients, and as bidirectional suppressors, which protect against both positive and negative high voltage transients. t ransient voltag e suppressors are avail - able in a wide range of standoff and breakdown voltage ratings. the tvs should be sized with the lowest breakdown voltage possible while not conducting in the functional range of the current output. it is recommended that all field connected nodes be protected. microprocessor inter facing microprocessor interfacing to the ad5737 is via a serial bus that uses a protocol compatible with microcontrollers and dsp processors. the communication c hannel is a 3 - wire minimum interface consisting of a clock signal, a data signal, and a latch signal. the ad5737 requires a 24 - bit data - word with data valid on the falling edge of sclk. the dac output update is i nitiated either on the rising edge of ldac or, if ldac is held low, on the rising edge of sync . the contents of the registers can be read using the readback function. ad5737 - to - ads p- bf527 interface the ad5737 can be connected directly to the sport interface of the adsp - bf527 , an analog devices, inc., blackfin? dsp. figure 63 shows how the sport interface can be connected to control the ad5737 . ad5737 sync sclk sdin ldac sport_tfs sport_tsclk sport_dt0 gpio0 adsp-bf527 10067-080 figure 63 . ad5737 -to- adsp - bf527 sport interface layout guidelines grounding in any circuit where accuracy is important, careful consider - ation of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5737 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5737 is in a system where multiple devices require an agnd - to - dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the gndsw x pin and the ground connection for the av cc supply are referred to as pgnd. pgnd should be confined to certain areas of the board, and the pgnd - to - agnd connection should be made at one point only. supply decoupling the ad5737 should have ample supply byp assing of 10 f in parallel with 0.1 f on each supply , located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f cap - acitor s should have low effective series resistance ( esr) and low effective series inductance (esl), such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents d ue to internal logic switching.
data sheet ad5737 rev. b | page 41 of 44 traces the power supply lines of the ad5737 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital groun d to prevent radi - ating noise to other parts of the board and should never be run near the reference inputs. a ground line routed between the sdin and sclk trac es helps reduce crosstalk between them (not required on a multilayer board that has a separate g round plane, but separating the lines helps). it is essential to minimize noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on oppo - site sides of the board should run at right angles to each other to reduce the effects of feedthrough on the board. a microstr ip technique is by far the best method, but i t i s not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground plane, a nd signal traces are placed on the solder side. dc - to - dc converters to achieve high efficiency, good regulation, and stability, a well - designed printed circuit board layout is required. follow these guidelines when designing printed circuit boards (see figure 55): ? keep the low esr input capacitor, c in , close to av cc and pgnd. ? keep the high current path from c in through the inductor (l dcdc ) to sw x and pgnd as short as possible. ? keep the high current path from c in t hrough the inductor (l dcdc ), the diode (d dcdc ), and the output capacitor (c dcdc ) as short as possible. ? keep high current traces as short and as wide as possible. the path from c in through the inductor (l dcdc ) to sw x and pgnd should be able to handle a mini mum of 1 a. ? place the compensation components as close as possible to the comp dcdc_x pin. ? avoid routing high impedance traces near any node connected to sw x or near the inductor to prevent radiated noise injection. galvanically isolate d interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common - mode voltages that may occur. the analog devices i coupler ? product s can provide voltage isolation in excess of 2.5 kv. the serial loading structure of the ad5737 makes it ideal for isolated interfaces because the number of inter - face lines is kept to a minimum. figure 64 shows a 4 - channel isolated interface to the ad5737 using an adum1411 . for more information, visit www.analog.com . seria l clock out t o sclk encode decode seria l d at a out t o sdin encode decode sync out encode decode contro l out encode decode microcontroller adum14 11 t o sync t o ldac 10067-081 v ia v oa v ib v ob v ic v oc v id v od figure 64 . 4- channel isolated interface to the ad5737
ad5737 data sheet rev. b | page 42 of 44 industrial hart capa ble analog output application many industrial control applications hav e requirements for accurately controlled current output signals, and the ad5737 is ideal for such applications. figure 65 shows the ad5737 in a circuit design for a hart - enabled output module, specifically for use in an industrial control application. the design provides for a hart - enabled current output, with the hart capability provided by the ad5700 / ad5700 -1 hart m odem, the industrys lowest power and smallest footprint hart - compliant ic modem. for additional space - savings, the ad5700 -1 offers a 0.5 % precision internal oscillator. the hart_out signal from the ad5700 is attenuated and ac - coupled into the chartx pin of the ad5737 . such a configuration results in the ad5700 hart modem output modulating the 4 ma to 20 ma analog current without affecting the dc level of the current. this circuit adheres to the hart physical layer specifications as defined by the hart com munication foundation. for transient overvoltage protection, a 24 v transient voltage suppressor (tvs) is placed on the i out /v out connection. for added protection, clamping diodes are connected from the i out _x /v out _x pin to the av dd and gnd power supply p ins. a 5 k current limiting resistor is also pla ced in series with the +v sense_x input. this is to limit the current to an acceptable level during a transient event. the recommended external band - pass filter for the ad5700 hart modem includes a 150 k resistor, which limits current t o a sufficiently low level to adhere to intrinsic safety requirements. in this case, the input has higher transient voltage protection and should, therefore, not require additional protection circuitry, even in the most demanding of industrial environments. ad5737 10067-065 mcu uart interface 10f 10k? 10f 0.1f 0.1f 0.1f 0.1f 2.7v to 5.5v dv dd av dd reset alert fault clear sync ldac sclk sdin sdo dgnd ad5700/ad5700-1 txd v cc rxd rts cd hart_out +15v av cc +15v sw(x4) v boost (x4) iout b,c,d chart b,c,d iouta d2 d1 d3 r p r l refout refin chart a gnd 22nf c1 47nf c2 4.20ma currentloop adc_ip ref gnd 1f 150k? 150pf 300pf 1.2mq 1.2mq figure 65 . ad5737 in hart configuration
data sheet ad5737 rev. b | page 43 of 44 outline dimensions compliant to jedec standards mo-220-vmmd-4 0.25 min 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 ty p 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max sea ting plane pin 1 indic at or 7.25 7.10 sq 6.95 pin 1 indic at or 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. top view exposed pa d bot t om view 9.10 9.00 sq 8.90 8.85 8.75 sq 8.65 04-10-2012-c figure 66 . 64 - lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp - 64 - 3) dimensions shown in millimeters ordering guide model 1 resolution (bits) temperature range package description package option ad5737 acpz 12 ?40c to +105c 64-l ead lfcsp_vq cp -64 -3 ad5737 acpz -rl7 12 ?40c to +105c 64-l ead lfcsp_vq cp -64 -3 1 z = rohs compliant part.
ad5737 data sheet rev. b | page 44 of 44 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10067 -0- 5/12(b)

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